Semiconductor integrated circuit (IC) fabrication involves forming multiple material layers with designed patterns on a semiconductor wafer. Those patterned material layers on the semiconductor wafer are aligned and configured to form one or more functional circuits. Photolithography systems are used to pattern a semiconductor wafer. When semiconductor technology continues progressing to circuit layouts having smaller feature sizes, a lithography system with higher resolution is need to image an IC pattern with smaller feature sizes. An electron-beam (e-beam) system is introduced for lithography patterning processes as the electron beam has wavelengths that can be tuned to very short, resulting in very high resolution. An e-beam lithography can write small features to a wafer but takes longer time. The corresponding fabrication cost is higher and cycle time is too long. Multiple e-beam lithography is introduced and it reduces the cycle time. However, in the raster-scan multiple e-beam lithography, it is limited to only single exposure dosage. For some hot spots in the IC design layout, the pattern contrast is poor and the process window is small.
It is desired, therefore, to provide an e-beam lithography method and a system for e-beam lithography pattern in IC fabrication to address the above issues.